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SmartDV™ Technologies, the leader in Design and Verification Intellectual Property (IP), today unveiled its broad portfolio of memory Design and Verification solutions including Memory Models, Verification IP and Design IP available for most memory types and derivatives.
“Memories are ubiquitous in system design and the ability to efficiently model, design and verify them is critical,” states Deepak Kumar Tala, SmartDV’s managing director. “SmartDV invests heavily in supporting all three of these memory-targeted solutions and a reason why our relationships with the largest memory vendors are our priority. They are built on our expertise and customer support, helping us maintain our ability to offer a large selection of Memory Models, Design IP and Verification IP.”
The SmartDV portfolio provides memory controller Design IP for all derivatives of DDR, LPDDR and Flash and supports the DDR PHY Interface (DFI) specification. Memory models and Verification IP are available for DDR, GDDR, ONFI, TCAM, FLASH, HBM, non-volatile memories and DIMM, and others.
SmartDV offers its memory models complete with a Memory Verification IP suite that incorporates the Controller Verification IP agent and Memory Model with its slave interface. The SmartDV Controller Verification IP agent helps verify an actual memory DUT and the SmartDV Memory Model helps verifying a Memory Controller DUT.
Its SmartCompiler generates Memory Models by using the memory part number as input, ensuring delivery of memory model to fit the exact requirement of the development flow.
SmartDV memory models support most methodology and language environments, such as SystemVerilog, VMM, OVM, UVM, SystemC, Verilog and Specman.
Availability and Pricing
The SmartDV Memory Model portfolio is available now.
Pricing is available upon request.
Email requests for more information.