Tower Semiconductor
Tower Semiconductor Reports First Quarter 2022 Record Revenue of $421...
The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams while preserving their software investment; it’s just not practical to start over when the current or next design requires a higher or lower level of throughput.
In this webinar we will highlight some of the sensor fusion applications driving the need for more efficient digital signal processing, often combining classical filtering operations and AI-based decision making. Featuring the Synopsys ARC® VPX DSP family, we will explain key functions that can be optimized to handle a spectrum of sensor fusion workloads, while adhering to a single programming environment.
Join the brightest minds for networking, and exploration of trends, technologies, and breakthrough achievements that will deliver a smarter, more connected, and sustainable world.
Discover the power of simulations, HPC and AI/Data Analytics that applied to the most complex research and development challenges. Learn about practical applications of the latest Altair technology and how to deploy it throughout the product development cycle.
Changing tomorrow, together.
Industry consolidation and cost streamlining eliminated many proprietary processor architectures and channeled alignment to a subset of standardized instruction set architectures (ISAs). Today, many embedded applications such as those found in artificial intelligence (AI), automotive and storage segments require increased bandwidth and memory address space expansion. As Moore’s law slows, design teams seek different ways to deliver unique solutions for these applications while maintaining power, performance, and area (PPA) goals. Designers commonly start with a standard ISA based processor to benefit from common tools, and software ecosystem, but look to extend the architecture to meet their product’s unique needs. This discussion will explore how highly extensible processor architectures can enable designers to meet their application requirements and provide SoC differentiation.
As process modes become smaller, designs become bigger and more complex. This translates to more challenging power, performance, and area (PPA) targets.
In this full-day, in-person seminar, we will discuss the entire portfolio of the Cadence® integrated digital full flow, which offers innovations that go across individual tool boundaries by integrating core engines and key technologies that allow you to beat your PPA goals ahead of schedule.
Have your questions answered by Cadence experts from the product marketing and product engineering teams in the UK and the US—the people who are directly involved in architecting the technologies.
You are invited to join us for this unique opportunity.
a unique webinar on chip design and beyond.
Expert presentations, various topics, live Q&A.
SemIsrael Expo 2021 is the premier professional semiconductor event in Israel.
The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry.
The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries, design houses, labs and universities.
The event will be hosted at Avenue Convention and Events Center on November 29, 2022.
SemIsrael Expo events are produced by SemIsrael – The Israeli Semiconductor Portal.