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PCI Express 6.0 – Physical Layer Characterization of a Low Latency PAM4 Link at 64GT/s, David Bouse

27/9/2022

David Bouse, Principal Technology Lead from Tektronix, will provide an update on PCI Express 6.0 with an emphasis on Physical Layer design and characterization at 64 GT/s PAM4. The emergence of new data center applications requiring AI/ML, high-performance computing, and increasing Networking bandwidths are some of the drivers of this latest inflection point. New protocols such as CXL leverage the PCIe protocol layer and enable cache coherency for increasing memory demands. The legacy CEM form factor has managed to maintain backward compatibility propped up by PCB layout optimizations and we’ve seen the emergence of numerous form factors including M.2 and EDSFF “Ruler” reach high volume manufacturing with fewer interoperability standardizations. David’s talk will bring clarity to this healthy yet complex ecosystem with a deep dive into the latest methodology for characterizing transceivers at 64 GT/s supporting different protocols across the numerous form factors expected in the years to come.

BIO:

David Bouse is a Principal Technology Leader at Tektronix with expertise in highspeed SERDES including transmitter and receiver test methodologies, digital signal processing algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture. David represents Tektronix within the PCI-SIG and CXL standard bodies contributing to the Electrical and Serial Enabling groups participating in the Base, CEM, and test specification development. Pathfinding is his specialty for stressed eye calibration techniques and transmitter characterization to advance data rate speed. David leads numerous gold test suites at the PCI-SIG compliance workshops and helps to develop future programs with an emphasis on test and measurement correlation. David supports real time oscilloscope and receiver hardware test development and is the technical leader for the Tektronix PCI Express and CXL solutions. He authored the PCI Express 4.0 Physical Layer test specification while previously at Intel, designed PCIe/USB test fixtures, and was the lead software developer for the SigTest compliance and validation tool.

http://tektronix.com/

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