Synopsys Boosts 5G SoC Development Productivity with New RF Design...
With the convergence of processing requirements across multiple different industry verticals, the need to support flexibility and scalability in new designs is even more essential. Whilst virtualized/containerized workloads running on CPUs are central to, and simplify many of these new designs, the need for workload acceleration is essential to meet overall power, throughput and latency requirements. Achronix Semiconductor’s presentation will review how FPGA and embedded FPGA (eFPGA) IP resources can be utilized to provide support for various acceleration offload requirements including protocol translation, security and ML workloads. Achronix’s unique 2D NoC interconnect allows FPGA fabric resources to be split into logical partitions that appear as a homogeneous block of resources, which can be virtualized into multiple FPGA sub-elements, each supporting its own function. The 2D NoC provides a low latency, transparent conduit between external memory, I/O interfaces and FPGA logic resources. After attending this presentation, you will understand the benefits of FPGA and eFPGA IP architectures and how they can be used to implement virtualized accelerator blocks in your design.
Kent Orthner has worked in the IP, semiconductor, and embedded industry for over 20 years, with a focus on all aspects of interconnect, IP interoperability, and FPGA design. At Achronix, Kent contributes to leading-edge FPGA architecture and SoC integration. Prior to joining Achronix, Kent was the Vice President of Engineering at Arteris, where he developed and released the highly scalable and configurable Ncore cache-coherent SoC interconnect IP. Before that, Kent worked at Altera for 11 years, where he led the development of the Qsys System Integration platform and the SystemConsole debug infrastructure. Kent holds a B.A.Sc. from the University of Ottawa, and a M.Eng from Carleton University, in Computer and Electrical Engineering, respectively.
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