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With advanced nodes & larger chip sizes, comes the challenge of longer test times & guaranteeing reliable silicon operation over its entire lifecycle. Today’s SoC’s have many mission critical applications which require a very low defective-parts-per-million (DPPM) metric. There are two ways to guarantee low DPPM – Continuous testing and monitoring of semiconductor devices throughout their lifecycle & increased test coverage. At the same time there is pressure to reduce number of pins on the SOC, making it difficult to meet test time and cost goals. High-speed functional interfaces such as PCIe and USB can double duty as high-speed test access interfaces addressing above mentioned challenges. In this presentation, we will highlight a novel solution that leverages existing Functional Protocol based High Speed interface for testing/monitoring and provides a consistent portable method to test silicon throughout its lifecycle.

BIO:

Tal Kogan has joined Synopsys 3 years ago as the manager of the European Test team. Before that, Tal was Mobileye DFT Lead, and served as DFT manager at Intel & Zoran.