Semisrael Videos

IP QA Best Practices, by Siddharth Ravikumar, Technical Product Manager, Solido IP Validation, Siemens EDA

15/5/2023

As modern System-on-Chips (SoCs) become larger and more complex, design IPs have become essential building blocks. Design IPs allow for modularization and re-use of design components, which is crucial for managing the increasing scale and complexity of SoCs. However, IP data library can be vast and contain multiple views and formats, leading to potential inconsistencies that may be difficult to identify.
A robust QA framework for design IPs which can detect inconsistencies early in the flow is a crucial component for successful silicon production. Implementing a proper QA methodology can ensure that critical metrics such as consistency, accuracy, and completeness are met, leading to better silicon quality and shorter production schedules.
A robust IP QA framework should possess the following capabilities:
Design- and technology-agnostic IP QA: The framework should focus on identifying issues early in the flow, regardless of the underlying design methodology or technology node being used.
Comprehensive validation coverage: The validation methodology should cover a wide range of checks to ensure thorough verification.
Adaptability to changing specifications: Performance and specifications may change at each revision made to the design IP. Therefore, the QA methodology must have the ability adapt to these changes.
Flexibility for adding functionality: To support a wide range of use cases, the QA methodology should be extensible, and allow for the addition of custom functionality to complement existing built-in checks.
In this webinar, we will explore the different challenges and risks in IP QA and discuss how a robust IP QA tool can mitigate them. We will delve into the various checks, such as syntax checks, in-view and cross-view consistency checks, timing arc checks, layout comparisons (e.g., LEF versus GDS), and others, that can identify potential issues early in the design flow and improve the overall quality of design IP.
BIO:
Siddharth Ravikumar is a seasoned professional with over 11 years of experience in the semiconductor industry. He has a background in front-end design and verification, as well as test engineering. He currently serves as a Technical Product Manager for Solido IP Validation at Siemens EDA, where he brings his expertise to develop and launch innovative products. Siddharth holds a Master’s degree in Electrical Engineering from Santa Clara University.

More info: https://eda.sw.siemens.com/en-US/

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