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Timing Constraints and Physical Planning Platform – Excellicon focus is on helping designer from early stages to ensure timing constraints are properly developed and verified prior to handoff to physical design implementation. Product portfolio is designed to ensure quickest and most efficient path to timing closure and reducing unnecessary iterations. Our products facilitate automatic generation of timing constraints including constraints promotion, demotion, budgeting, verification, equivalence checking etc. On the physical side, the products provide capabilities to perform early floorplan verification, Clock tree analysis, floorplanning and RTL restructuring.
Over 20 years of chip design experience, designing complex SOCs in networking, communications, imaging, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon, Himanshu served as an advisory board member of several EDA companies. His experience is crucial to ensuring development of tools fit for everyday design by front and back-end engineers and shaping the future direction of Excellicon
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