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Analog Design Flow and Porting: an Overview by Milos Capin​, Analog Engineer, HDL Design House


Increasing complexity of SoC designs and shrinking of process nodes has enabled the implementation of very sophisticated digital designs with increasing number of gates. However, analog design plays a very important role in SoC design. Apart from dedicated analog integrated circuits, IPs including voltage regulators, PLLs, transceivers, etc. are vital building block of almost any SoC design. This presentation will be an overview of some basic steps and problem associated with the analog design. ​


Milos Capin is Analog Engineer at HDL Design House more than 7 years. He is an expert in domain of SoC Analog Design. He has experience in analog and mixed signal IC design in various technology nodes, working on 180nm HV planar node down to the most advanced nodes. Through the past, HDL DH analog team of engineers gained experience in design of different analog modules used in the variety of applications from HV automotive to High-Speed SERDES, such as: PLL, Bandgap reference, ADC, LDO, OpAmp, USB PHY etc.

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