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The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification.
This presentation outlines methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters. The focus is on more complex RISC-V processors, and methodologies that account for asynchronous events: interrupts and debug operations, plus hardware configurations including multi-issue and Out-Of-Order pipelines, multi-hart processors, vector extensions and custom instructions.
Larry is currently VP Worldwide Sales at Imperas Software Ltd., and previously ran worldwide sales at EDA companies including Calypto and Verisity Design. Larry has about 30 years in software tools and EDA, plus time spent in infrared systems engineering. Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University where he was an Entrepreneur-in-Residence during Fall 2006, when he developed and taught the course on Entrepreneurial Sales.
More info: https://www.imperas.com/
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