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The open standard RISC-V Instruction Set Architecture (ISA) is driving a new wave of innovation through the SoC and hardware design teams. With RISC-V it is possible to build an optimized processor with just the right mix of features and functions, using standard extensions and custom instructions that leverage the growing ecosystem of software and tools. RISC-V provides developers new design freedoms and flexibility, but with these innovations the challenge will be to achieve time-to-market with a fully verified, production ready RISC-V implementation. This talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications, including the innovations in processor designs with features such as: out-of-order pipelines, hardware multi-threading, multi-hart, custom extensions and advanced privileged modes, plus vector accelerators. Key updates will focus on functional coverage, Verification IP (VIP) and testbenches for asynchronous events, with examples from customers, partners and users at the forefront of RISC-V adoption.
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University’s Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.
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