Tagged: RISC-V

In this contribution we will describe Semidynamic’s RISC-V IP comprising its advanced family of out-of-order cores (code named Atrevido) and…

The rapid adoption of the open standard RISC-V instruction set architecture (ISA) has focused on the ISA specification and various…

While we are only scratching the surface of the incredible impact AI/ML is having on organizations as they adopt these…

For SoC designers adopting RISC-V, tackling the processor DV tasks presents some new challenges. The established SoC flows have some…

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