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December 6-8, 2021, Moscone Convention Center, West Hall, Booth #1351
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.
At the Design Automation Conference (DAC), TCI will introduce new synthesizable PLLs and DLLs that will continue to raise the bar for timing IP features, performance and flexibility for a wide range of customer applications. For over 23 years, TCI has led the industry with the regular introduction of new timing architectures and IP design types that have defined the timing IP category, and offered chip designers a wide variety of solutions to their timing needs. TCI is proud to introduce our latest timing IP, the synthesizable Precision PLL, micro PLL and micro DLL. Each is available in the latest process nodes and back to 28nm.
The synthesizable Precision PLL generates multiple precision clocks supporting any modulation scheme from almost DC to 10GHz. The outputs can be independently dynamically programmed cycle-by-cycle to any clock period and the clock frequency can be a precise ratio of floating point numbers times the reference frequency. The integrated phase noise is better than 500ps RMS. It is ideal for SerDes, processor and DVFS applications.
The synthesizable micro PLL is a small synthesizable general-purpose PLL that multiplies the reference clock by any integer or fractional-N value from 1 to 500K. It supports reference clock frequencies as low as 32KHz and output frequencies as high as 3GHz. It can stay locked to the reference clock while it changes over a 10:1 frequency range. Because it is synthesizable, it can support spreading as well as other modulation profiles. It is relatively low power, very fast locking and can quickly restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master and multiple slaves topology. It can support reference frequencies typically in the range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range while providing 9-bit accuracy in slave delay programming. Slave delays can be changed glitch free and the DLL can quickly restart from a sleep mode. It has a very small zero code offset that can be precisely cancelled.
TCI will also showcase its high performance, silicon proven DDR PHY with fully automatic training managed by a light weight special purpose processor, and remarkable physical flexibility to adapt to each customer’s die floorplan and package. The DDR PHY has been developed using the powerful custom design automation tools that have made TCI’s line of high performance PLLs and DLLs a staple in the semiconductor industry for over 23 years. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3, and LPDDR3 protocols. The availability of this silicon proven PHY means customers can now license a PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings.
The DDR PHY supports up to LPDDR5, and has undergone extensive silicon testing in our lab and has achieved DDR4 3200Mbps and DDR3 2133Mbps in TSMC 28nm HPC+ across PVT without bit errors. TCI went to great lengths to implement the DDR 4/3 PHY test chip just as our customers would implement a product chip. We used industry standard tools to synthesize, place and route the test chip, incorporated a Northwest Logic controller and Aragio Solutions DDR and General Purpose IOs, utilized custom high quality test boards and sockets, and used Micron memories. Taking this approach allowed us to experience and evaluate every aspect of the implementation of the PHY so we can better support our customers.
During the show, we will be giving short presentations and demos of the PHY in action. This will be a great opportunity to ask questions and learn what makes a TCI DDR PHY hard macro one special piece of IP.
We will also feature our complete line of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, Ultra and IoT PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant, reusable and available for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 4nm.
As always, we are glad to discuss your IP needs, including IP selection, IP integration, IP reuse, jitter specifications and silicon testing, so please stop by our booth #1351 and spend some time with the timing experts!
When and Where
Moscone Convention Center, West Hall, San Francisco, CA
True Circuits Booth #1351
Monday – Wednesday, December 6-8, 10:00 AM to 6:00 PM
For more information about True Circuits’ PLLs, DLLs and DDR PHYs, please visit www.truecircuits.com.
For more information about the Design Automation Conference, please visit www.dac.com.