Market Leaders Collaborate with Synopsys to Realize Gains of Generative...
Addressing the software bring-up, power optimization and debug challenges of complex billion-gate and multi-die systems, Synopsys, Inc. (Nasdaq: SNPS) today launched the Synopsys ZeBu® Server 5 emulation system. Compared to the previous generation ZeBu system, Synopsys ZeBu Server 5 supports 1.6x greater capacity while delivering 2x higher throughput and 2x better emulation performance with less than half of the power consumption.
More than 400 Billion Gates of Synopsys ZeBu Server 5 Emulation System Sold in First Year, Accelerating Deployment of Complex SoCs and Multi-Die Systems
“Today’s software-driven systems—like the electronics found in an advanced car or VR headset—demand massive computing power for cutting-edge algorithms required to replicate complex scenarios in the real world or metaverse,” said Ravi Subramanian, GM of Synopsys Systems Design Group. “Getting these products right means thoroughly testing the software running on your chip for over tens of billions of cycles on an emulation system before production. Synopsys’ ZeBu Server 5 delivers the highest performance emulation system in the world, with over 400 billion gates of chip capacity sold to customers all over the world, making it one of the most successful emulation products in the industry.”
Synopsys ZeBu Server 5 is the latest in the company’s market-leading hardware-assisted verification portfolio and is available now. Learn more at: https://www.synopsys.com/verification/emulation/zebu-server.html
Co-Optimizing Hardware and Software for System Success
For the verification workloads of billion-gate designs and multi-die systems, performance, capacity and reliability are key to achieving faster software bring-up and hardware development. Digital twins play an important role, providing a digital replica of an electronics system used throughout the product lifecycle for software bring-up, power analysis and SW/HW validation. Semiconductor and system companies can collaborate more closely with digital twins, together ensuring that designs will work as intended and avoiding costly silicon respins. The additional horsepower of Synopsys ZeBu Server 5 will advance electronics digital twin capabilities, enabling designers to speed up development of production-ready silicon. Availability on the cloud provides verification engineers the flexibility to scale up and down as their projects demand.
“While multi-die systems designs are helping to enable systems to meet the aggressive demands of compute-intensive applications, getting these highly complex systems to market quickly is challenging,” said Alex Starr, Corporate Fellow at AMD. “Synopsys ZeBu Server 5 was designed from the ground up to utilize the AMD Virtex UltraScale+ VU19P FPGAs to achieve fast emulation speeds at the demanding design capacity levels we see today. This enables us to meet the exacting market requirements for our most challenging designs.”
“For billion-gate designs now required for compute-intensive applications, an exhaustive and accelerated debug process is only possible by using electronics digital twins,” said Hyundon Kim, principal engineer at Samsung. “With its high capacity and throughput, Synopsys ZeBu Server 5 provides an ideal solution to perform pre-silicon validation of our Exynos SoC products and enable early software bring-up and hardware development.”