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Silvaco Group, Inc. (Nasdaq: SVCO) (“Silvaco”), a provider of AI-enabled TCAD and EDA solutions, and SIP solutions that enable semiconductor design and digital twin modeling through AI software and innovation, announces the immediate availability of Mixel™ MIPI® C-PHY™/D-PHY™ Combo Universal IP on TSMC’s industry-leading N2P process. The MIPI C-PHY IP supports the v2.1 specification, and the MIPI D-PHY IP supports the v3.6 specification.

The Mixel MIPI C-PHY/D-PHY Combo Universal IP is a physical layer specifically optimized for low power, low leakage, and minimal area. In an industry first, this IP supports MIPI D-PHY with embedded clock mode (ECM), a new mode first released in the MIPI D-PHY v3.5 specification and carried forward in v3.6. The Mixel IP supports speeds up to 3.0 Gbps per lane in D-PHY mode over two wires, compared to a traditional MIPI D-PHY interface requiring a minimum of four wires with a forwarded-clock mode. The combo IP also supports the MIPI C-PHY v2.1 specification at 3.0 Gsps per trio, an equivalent data rate of 6.84 Gbps/trio. As a universal IP, it is the superset configuration that includes a high-speed transmitter and receiver supporting full-speed loopback.

This IP was specifically designed for use cases where power efficiency, minimal area, low EMI, and low heat dissipation are critical—without compromising performance. Such applications include augmented reality (AR) glasses and wearables. By leveraging the latest features available in the MIPI specification, the Mixel MIPI C-PHY/D-PHY ECM combo achieves the same throughput with 25% fewer wires compared to a standard MIPI C-PHY/D-PHY combo with a forwarded-clock D-PHY IP. The reduced wire count is beneficial for use cases with extreme form factor constraints such as AR glasses where all wires need to fit inside a lens frame.

“Mixel, now part of Silvaco, has long been a valued contributing member of the MIPI Alliance,” said Hezi Saar, chair of MIPI Alliance. “It is great to see these two companies combining their strengths to deliver MIPI C-PHY and D-PHY solutions on TSMC’s advanced N2P process.”

Mixel was the first IP provider to demonstrate silicon-proven MIPI C-PHY with its MIPI C-PHY/D-PHY combo IP in 2016. Mixel’s MIPI PHY IP has been silicon-proven in 10 different TSMC process nodes including N6 and N5.

“We are excited to announce immediate availability of our next-generation MIPI C-PHY/D-PHY IP on TSMC’s N2P process, the advanced Nanosheet technology delivering industry-leading performance and energy efficiency,” said Andy Wright, SVP and GM of Silvaco Semiconductor IP. “This demonstrates our ongoing commitment to expand our portfolio to the leading-edge processes, providing customers with high-performance, reliable solutions for next-generation applications.”

Availability:

Mixel MIPI C-PHY/D-PHY Combo IP is available now on TSMC N2P process. For more information on Mixel’s IP portfolio, please visit https://mixel.com/ip-cores/.