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Real Intent, Inc., today announced Verix DFT, a full-chip, multimode DFT static sign-off tool. Verix DFT’s comprehensive set of fine-grained DFT rules help designers to rapidly identify design violations and improve scan testability and coverage.
Verix DFT is deployed throughout the design process: 1) during RTL design, as part of addressing asynchronous set/reset, clock and connectivity issues early, 2) after scan synthesis, to check for scan chain rule compliance, and 3) following place & route to assess and correct issues with scan-chain reordering or netlist modification.
Multimode Reduces DFT Static Sign-off by Weeks
Verix Multimode DFT can reduce static sign-off time by several weeks. The savings are gained from lower setup time, runtime speedup, and the reduced engineering debug and violation fixing due to consolidated reporting.
In a single run, the tool can analyze:
“Running DFT static sign-off repeatedly to verify each ATPG partition and each constraint set is extremely time consuming,” said Prakash Narain, President and CEO of Real Intent.
Narain continued, “Additionally, much of design for testability analysis today occurs late in the cycle, when it is far more expensive to find and fix errors. Real Intent Verix DFT’s multimode design for testability static sign-off can be used early and at different design stages to reduce DFT static sign-off time by weeks and improve scan testability and coverage.”
Robust coverage, Fine-grained rules, and Root Cause Analysis
Verix DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success.
In addition to its multimode analysis capability, Verix DFT has:
Fault Coverage Estimation Option
Verix DFT has an additional tool option for fault coverage estimation. When the option is enabled, it will provide fault coverage for each test-mode, along with a rollup of overall scan test fault coverage estimation.
By automatically estimating the fault coverage for each test mode, the user can better prioritize violation debug order and assess readiness for sign-off.
For more information on Verix Multimode DFT, please visit: https://www.realintent.com/design-for-testability-verix-multimode-dft/