Market Leaders Collaborate with Synopsys to Realize Gains of Generative...
In a continuing commitment to enabling industry-leading solutions for the semiconductor market, Fraunhofer IIS/EAS, leading-edge applied research institute in the field of advanced package solution design, and Achronix Semiconductor Corporation, the industry’s only independent supplier of high-end FPGAs and eFPGA IP solutions, are entering today in a partnership to build a heterogeneous chiplet solution to validate performance and interoperability in advanced high-performance system solutions. The Fraunhofer institute provides system concepts, design services and fast prototyping in most advanced packaging technologies and will make use of Speedcore™ eFPGA IP from Achronix in its next project. The multi-chip system solution will be composed of several chiplets that will be used to explore chip-to-chip transaction layer interconnects such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe).
Collaboration to create an eFPGA-enabled chiplet solution aimed at validating next-generation chip-to-chip interconnect technology.
Chiplets are rapidly being adopted for high-performance, heterogeneous multi-chip solutions and enable lower latency, higher bandwidth and lower cost than discrete devices connected via traditional interconnects on a printed circuit board. One key application that will be covered in this project is the connection of high-speed ADCs together with Achronix® eFPGA IP for preprocessing in radars as well as wireless and optical communication. Achronix Speedcore eFPGA IP is playing an important role in this application with low latency and reconfigurability while delivering high-performance data acceleration required in many applications.
The result of this project will create a demonstration platform suitable for applications such as 5G/6G wireless infrastructure, ADAS and high-performance test and measurement equipment. The findings of this cooperation will be communicated in a later press release and will be of interest to all semiconductor market actors seeking interface compatibility with their semiconductor chiplets.