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Cadence Design Systems, Inc. (Nasdaq: CDNS), a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE™), today announced that Samsung Foundry has qualified the Cadence® Integrity™ 3D-IC platform’s 2D-to-3D native 3D partitioning flow. Using the new flow, customers can partition existing 2D designs into 3D memory-on-logic configurations and achieve better power, performance and area (PPA) with a homogeneous 3D stack when compared with the original 2D design. The flow also provides robust 3D-IC system planning, implementation and early analysis capabilities for the partitioned design, which is ideal for customers creating complex, next-generation hyperscale computing, mobile, automotive and AI applications.
Integrity 3D-IC is Cadence’s next-generation multi-chip design solution, integrating silicon and package planning and implementation with system analysis and signoff to enable system-driven PPA optimization
Hitting a memory wall where RAM access cannot keep pace with CPU execution speed causes the overall system to slow down due to memory latency. One way to overcome this is to place memories on top of the logic in a homogenous stacking configuration. The configuration, when mounted on the same package, reduces wirelength and area and speeds up memory access, thus helping to improve the performance of the CPU core.
The Integrity 3D-IC platform’s 3D partitioning enables the user to separate out memory macros and standard cells and place them on two different dies within a 3D homogeneous stack. The automated flow performs partitioning and full implementation of the 3D stack while building connections between the macros and standard cells. Once the contents of each die are finalized, the system and package can be implemented in the Integrity 3D-IC platform, enabling bump planning, implementation, co-design with other dies, and early analysis of thermal, power and static timing analysis (STA).
“Customers faced with varying automated partitioning requirements for 3D-IC configurations can take advantage of this unique capability in Samsung Foundry’s MDI reference flow based on Native 3D partitioning in Cadence’s new Integrity 3D-IC platform to explore the effects of chip stacking,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “This successful cooperation between Cadence and Samsung provides customers with a partitioning, implementation and analysis flow for stacked 3D designs that enables them to reduce power consumption and area while improving overall system performance.”
“Through our ongoing collaboration with Samsung Foundry, we’ve collaborated to innovate in the area of multi-die implementation and deliver automated Native 3D partitioning flows,” said Vivek Mishra, corporate vice president, Product Engineering in the Digital & Signoff Group at Cadence. “Samsung Foundry’s advanced packaging for multi-die implementation, combined with Cadence’s unified Integrity 3D-IC platform, provides our mutual customers with robust multi-die solutions.”
The Integrity 3D-IC platform provides customers with a common cockpit and database, a complete planning system, seamless implementation tool integration, integrated system-level analysis capabilities and an easy-to-use interface and lets users co-design with the Virtuoso® Design Environment and Allegro® packaging technologies. The platform also includes a broader Cadence 3D-IC solution portfolio including the Voltus™ IC Power Integrity Solution for power delivery network (PDN) analysis, Celsius™ Thermal Solver for 3D thermal analysis, Tempus™ Timing Signoff Solution for 3D signoff timing and Pegasus™ Verification System for system layout-versus-schematic (LVS). For more information on the Integrity 3D-IC platform, please visit www.cadence.com/go/Integrity3DICpl.