Partners PRs

Baya Systems, a leader in high-performance system architecture and design tools, today announced it will participate in Andes RISC-V CON Silicon Valley. In a joint developer track session with Imagination Technologies and Andes Technology, Baya chief software architect Dr. Eric Norige and Imagination Director of Product Management Pallavi Sharma will present on heterogeneous system-on-chip (SoC) strategies designed to optimize performance for AI, machine learning and graphics-intensive workloads. This collaboration between Imagination, Baya and Andes combines GPU expertise with data-driven, system-level insights, empowering SoC designers to create efficient, scalable RISC-V platforms.

Technical session to explore memory hierarchy, CPU-GPU interaction and real-world integration strategies for accelerating AI and edge workloads

The session, “Unleashing the Power of Heterogeneous Computing,” will examine how real-time interaction between CPU and GPU subsystems impacts memory hierarchy, bandwidth allocation and latency. Attendees will gain insights into architecture-level decisions that influence frame rendering, AI inference efficiency and compute distribution in edge environments, and a software platform that can provide those insights early and continuously throughout the design process from concept to deployment.

“The complexity of modern workloads demands architectural agility,” said Norige. “By analyzing subsystem interaction and designing intelligent cache and memory hierarchies, we can maximize performance gains across AI and graphics domains—without over-engineering the silicon.”

Session highlights include:

• Cache and memory hierarchy analysis: Using Baya’s CacheStudio™ software, Norige and Sharma will demonstrate how developers can simulate cache architectures, evaluate memory access patterns and optimize coherence between CPU and GPU cores.
• Platform-agnostic integration: The session will show how CacheStudio supports integration of Imagination GPU IP and Andes RISC-V cores through a unified, modular environment that accelerates development while improving silicon area efficiency.
• AI and graphics use cases: Live demonstrations will model inference workloads and graphics pipelines to showcase how compute offload, memory arbitration and shared cache tuning can reduce latency and power usage while increasing throughput.

Technologies featured in the session:

• Baya Systems: Software-defined IP and architecture tooling for SoC and chiplet design, including workload simulation, cache and memory hierarchy modeling and interconnect optimization.
• Imagination Technologies: High-performance, low-power GPU IP designed for edge inference, industrial AI and advanced graphics.
• Andes Technology: A complete RISC-V IP portfolio, including out-of-order cores and performance modeling tools for system-level validation and optimization.

“Imagination is thrilled to collaborate with Baya Systems and Andes Technology to explore innovative SoC strategies. By combining our GPU expertise with system-level insights, we aim to empower developers to create efficient, scalable RISC-V platforms that meet the demands of modern AI and graphics workloads,” said Pallavi Sharma, Director of Product Management, Imagination Technologies.

“As RISC-V adoption grows, so does the demand for smarter, workload driven SoC design and optimization,” said Marc Evans, Director of Business Development and Marketing at Andes Technology. “This session is a great opportunity for developers to explore integration strategies that deliver real performance gains.”

The session will take place on Tuesday, April 29, 2025, from 3:30 p.m. to 4:30 p.m. PT at the DoubleTree by Hilton Hotel in San Jose, Calif. You can register to attend the event through Eventbrite.