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Andes Technology to Exhibit Groundbreaking RISC-V Solutions for AI and Automotive at RISC-V Summit North America 2023

Andes Technology Corporation (TWSE: 6533), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, announces its significant role as the diamond sponsor in RISC-V Summit North America, the prestigious annual event held from November 6 to 8, 2023 in Santa Clara. As a key contributor, Andes will deliver a keynote speech about AI/ML SoC solutions based on RISC-V and the latest on Andes RISC-V processors to enable them. Andes will also address three presentations and two demo talks focused on AI/ML solutions, automotive-grade IP, IOPMP, RISC-V vector technology and more. During the event, Andes will showcase its state-of-the-art RISC-V CPU IP offerings at booth  #D4.

Discover the cutting-edge insights from Andes’ presentations and explore live demonstrations of CPU IP technology at Booth # D4 and get your opportunity to seize lucky draw prizes, including mobile phones!

Andes President and CTO, Dr. Charlie Su, will present why RISC-V is a perfect solution to bring intelligence everywhere and introduce Andes product portfolio in the keynote speech “Taking RISC-V Intelligence Everywhere” on November 8 at 9:55 AM. Dr. Paul Ku, Deputy Director of Andes and chair of IOPMP task group, will give an update of IOPMP spec on November 6 at 14:55 PM. Chun-Nan Ke, Senior Technical Manager, will explore the Andes proposal for RISC-V matrix multiplication instructions which enhance significant performance for AI applications in his presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” on November 7 at 12:10 PM. Furthermore, Dr. Heng-Kuan Lee, Senior Manager, will discuss how to enhance efficiency and accuracy of computations in transformer models in “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” on November 7 at 15:15 PM. Lastly, Hubert Chung, FAE Manager, will deliver a demo talk “AI Solution – AndesAIRE, including HW and SW” on November 7 at 12:55-13:05 . Marvin Chao, Director of Solution Architect, will give the other demo talk “Andes Technology RISC-V Functional Safety Solutions” on November 7 11:10-11:20 AM at the demo theater.

In addition, Andes will proudly display development boards integrated with Andes-Embedded™ technology at the Developer Zone. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; high-performance industrial-grade microcontrollers from HPMicro; one of the first complete RISC-V microcontrollers with an embedded FPGA from Gowin; and an Arduino-compatible development board based on a wireless SoC from Andes. Seize the opportunity to understand how customers are working with Andes products for various applications by visiting the Developer Zone. Also, Andes will announce its new safety-enhanced core, D25F-SE, at the Launchpad session.

Besides presentations and live demo, RISC-V Board of Director and Andes CEO, Frankwell Lin, will join the Media Panel Luncheon ”RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” on November 7 at 13:00 PM. Join the discussion to discover the remarkable progress in the RISC-V ecosystem across diverse applications and witness how RISC-V is empowering companies with advanced design flexibility.

This event presents a valuable opportunity for RISC-V enthusiasts to reserve one-on-one discussion with Andes experts to explore RISC-V solutions in-depth. Andes invites you to visit booth #D4 at the RISC-V Summit and experience live demonstrations of its leading-edge CPU IP technology. Stop by Andes’ booth for a chance to win fantastic prizes, including mobile phones!

Details of Andes’ sessions during the RISC-V Summit are as follows:

November 6 (Member Day),  

  • 14:55-15:20 PM: Presentation “IOPMP Update” by Dr. Paul Ku, Deputy Technical Director

November 7 (Day 1),  

  • 12:10-12:30 PM: Presentation “Advancing AI Computing with Optimized Matrix Multiplication Techniques with RISC-V CPU” by Chun-Nan Ke, Senior Technical Manager , and Heng-Kuan Lee, Senior Manager
  • 13:00-13:55 PM: Media Panel Luncheon “RISC-V is HERE: Future Outlook with Invested RISC-V Leaders” by Frankwell Lin, Chairman and CEO
  • 12:55-13:05 PM: Demo “AI Solution – AndesAIRE, including HW and SW” by Hubert Chung, FAE Manager
  • 15:15-15:35 PM: Presentation “Enhancing Transformers: Accelerating Nonlinear Function Computation on RISC-V Vector Processor” by Heng-Kuan Lee, Senior Manager, and Simon Wang, Senior Technical Manager

November 8 (Day 2),  

  • 9:55-10:10 AM: Keynote “Taking RISC-V Intelligence Everywhere” by Dr. Charlie Su, CTO and President
  • 11:10-11:20 AM: Demo “Andes Technology RISC-V Functional Safety Solutions” by Marvin Chao, Director of Solution Architect

For more information, please visit the RISC-V Summit website.

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