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Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors

Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, is pleased to announce its partnership with WITTENSTEIN high integrity systems. This partnership is geared towards assisting developers in creating safety-critical solutions utilizing RISC-V technology such as AndesCore™ N25F-SE and D25F-SE.

In 2022, Andes Technology made a ground-breaking milestone by introducing the world’s first ISO 26262 fully compliant RISC-V processor IP – N25F-SE. Andes is committed to providing unwavering support to automotive professionals in creating safety-critical product lines. With an extensive portfolio of AndesCore™ processors, Andes has catered to diverse needs, ranging from performance efficient MCUs to high-performance AI/ML computations. To meet the demands of a wide range of automotive applications, Andes not only offers ASIL-B certified processor IPs but also is working on mission-critical ASIL-D certified processor IPs based on its well-established and popular CPU IPs.

Andes Technology is set to release its next highly anticipated ISO 26262 fully compliant processor, the D25F-SE – the safety-enhanced D25F. The D25F CPU IP, one of the most popular cores from AndesCore™ 25-series, is equipped with RISC-V P-extension (SIMD/DSP) ISA draft to efficiently manipulate multiple data sets simultaneously in a single instruction. Many endpoint applications processing digital signals such as voice, audio, image, and sensors as well as machine learning algorithms could get performance boost by the efficient SIMD/DSP instruction set. The AndesCore™ D25F-SE has already attracted some early customers, and is expected to become available in 2023 Q4 for general licensing.

WITTENSTEIN high integrity systems (WHIS) is a safety systems company that produces and supplies real time operating systems (RTOS) and platform solutions to the Automotive, Medical and Industrial sectors worldwide. The exciting partnership with Andes Technology allows RISC-V developers to use the renowned safety critical RTOS SAFERTOS® from WHIS with the latest AndesCore™ processors. The SAFERTOS® has been independently certified by TÜV SÜD to IEC 61508 SIL3 and ISO 26262 ASIL-D. It is used internationally wherever safety is paramount, delivering superior performance and reliability. Delivered with full source code and Design Assurance Pack, the SAFERTOS® is tailored for the customer’s unique processor/compiler combination and is very popular due to its impressive safety credentials and a straightforward upgrade path from the FreeRTOS, industry’s most popular open-source RTOS.

SAFERTOS® fully functional demos are available on the Andes development boards. Try SAFERTOS® for free today at: https://www.highintegritysystems.com/down-loads/manuals-datasheets/safertos-datasheet-downloads/. Andes development boards can be found for purchase on Mouser. For more information, please visit https://www.andestech.com/en/products-solutions/andeshape-platforms/.

“We’re proud to partner with Andes Technology and for SAFERTOS® to support AndesCore™.” said Andrew Longhurst, Managing Director for WITTENSTEIN high integrity systems. “We see a strong, compelling case for SAFERTOS® to support the RISC-V architecture. This combination of both technologies will provide an ideal platform for safety critical projects in the future.”

“The functional safety AndesCore™ IPs offer unique and competitive value to our customers demanding RISC-V processors with full certification,” said Dr. Charlie Su, Andes Technology’s President and CTO. “The exciting partnership with WITTENSTEIN high integrity systems enables us to provide solid solutions to our customers who are developing products for safety-critical applications. We are thrilled to partner with WITTENSTEIN high integrity systems as they bring the advantages of the SAFERTOS® to the RISC-V community, thereby enhancing the performance and robustness of safety-related RISC-V applications.”

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