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AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced that it has expanded the rules checked by its Verissimo SystemVerilog Testbench Linter to match the latest release (IEEE 1800.2-2020) of the Universal Verification Methodology (UVM) standard. These rules ensure that chip verification teams are fully compliant in their development of simulation models, testbenches, and tests.
This standard defines an application programming interface (API) used by verification engineers. The latest release expands the API to add functionality, and Verissimo includes rule checks for these new features as well some more subtle changes in the API. In addition, IEEE 1800.2-2020 has removed some outdated parts of the API, while marking other as “deprecated” and slated for removal in the future. Verissimo alerts verification engineers when they use deleted or deprecated functionality.
When Verissimo detects code that is not compliant with the latest standard, it proposes possible fixes for the verification team to consider. These suggestions provide assistance when writing new code and make it much easier to migrate old testbenches to the latest UVM version. All rule checks can be run in batch mode using Verissimo or interactively within the AMIQ EDA Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE).
“The UVM, like many standards, evolves significantly with each new version,” said Cristian Amitroaie, CEO of AMIQ EDA. “We are pleased to ensure that our users remain compliant by avoiding outdated aspects of the API while helping them to use new functionality quickly and easily.”
Availability and Pricing
The new features are available today in Verissimo. Pricing is available upon request.