World’s Biggest Chip Design Technology Users Event Reopens Live in...
Over the last few decades System on Chip (SoC) design size has dramatically increased, and more complexity has been introduced to deliver the desired functionality. Growing design sizes lead to the introduction of several asynchronous clocks which can result in the reporting of millions of clock domain crossings (CDC) at the IP/SoC level. This leads to significantly long CDC debug cycles. The manual approach to analyze and debug CDCs is time consuming and error prone. Synopsys machine learning (ML) based Root Cause Analysis (RCA) addresses these problems seamlessly.
This Synopsys webinar will cover how you can achieve 10X faster debug using Synopsys VC SpyGlass RTL signoff platform machine-learning technology.
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