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While chip designs have grown larger and more complex, demanding greater compute resources, the pressure to shorten design and verification cycles continues unabated. Design teams have found techniques and technologies to address these challenges, with many turning to cloud computing. Compared to many other industries, however, the chip design world has been slow to adopt the cloud. The reasons for this are understandable, with concern over security topping the list. But there are signs that the landscape is shifting. One of the biggest advantages that the cloud provides for doing chip design using electronic design automation (EDA) tools, is the virtually unlimited and advanced compute resources that deliver the capacity chip designers need. However, EDA tool flow and license management have remained a heavy lift. Synopsys has taken a fresh look at how the cloud can be utilized to bring greater agility to semiconductor design and verification. Read on to learn how you can take advantage of a new paradigm for EDA in the cloud. This article was originally published on the “From Silicon to Software” blog.
Chip Designers Are Moving to the Cloud, Too
Cloud computing is disrupting an array of industries, changing how goods and services are sold, how they’re priced, and much more. While security of intellectual property and data in the cloud was initially an area of concern, cloud providers have demonstrated how they can protect workloads through stringent security measures and processes.
Now, chip designers, too, are starting to migrate their high-volume workloads to the cloud. Large, established design houses are adopting cloud for peak workloads while startups are “born in the cloud.” Both are driven by the benefits the cloud provides—faster time to results, enhanced quality of results, and better cost of results—without having to invest in costly infrastructure.
As noted, an on-premise cloud model, where an organization hosts its own data center infrastructure, does come with challenges in terms of limited compute capacity as well as access to the most advanced compute resources. This model also doesn’t address license management challenges. Tool flows are complicated, encompassing licensing and legal agreements that often involve different vendors with different tool use specifications. Also, there are a fixed number of licenses available, and license servers represent single points of failure.
While the cloud has solved the compute resource challenge, tool licensing has remained a conundrum. This is an area Synopsys zeroed in on, exploring ways to close the gaps and enhance what was available in the industry. Many of the offerings on the market are point solutions, so there was also an opportunity to further simplify the landscape for design teams.
Synopsys Cloud: All-in-One Flexibility for Chip Designs of All Sizes
Our answer to these challenges is Synopsys Cloud, the industry’s first broad-scale cloud software-as-a- service (SaaS) solution. With Synopsys Cloud, deployed on the Microsoft Azure cloud computing platform, designers have access to our cloud-optimized design and verification products with pre- optimized compute capacity. It’s a single-source, pay-per-use model that provides flexibility for design projects of all sizes by enabling designers to tap into any cloud-optimized tool at any time and on any
scale. While gaining virtually limitless compute resources and tools, design teams also are freed from the need to manage a complex IT environment. A rich analytics dashboard provides insights on tool usage. To further simplify the environment, Synopsys is also working with major foundries to streamline the foundry collateral process, making it easier for customers to manage foundry data.
Customers who source compute infrastructure from public cloud service providers (“bring your own cloud,” or BYOC) can take advantage of Synopsys Cloud by leveraging the pay-per-use model or even running some workloads in the Synopsys Cloud SaaS environment. Once connectivity has been established between the on-prem and cloud environments to allow data transfer, these customers can simply run the same scripts and binaries for designated design and verification workloads. Usage is measured on an hourly basis and charges are based on activity.
SaaS customers do everything through the Synopsys Cloud portal, logging in to manage users, projects, and infrastructure. Tools for specific use models like timing analysis and physical verification are enabled applications in the SaaS environment, accessible via the portal.
Without constraints related to capacity or hardware, designers can change how they manage, schedule, and design EDA projects through the lifecycle of their chips. They no longer must commit to a certain number of tool licenses or a particular amount of compute resources before beginning a design. Instead, they can scale up or down as needed, when needed, deciding at any given moment how many instances of a tool are needed and to run them at any scale. As a result, customers can run more jobs faster,
taking advantage of the scalability and elasticity of the cloud. Jobs that previously took weeks to finish can now be completed in hours given the dynamic access to robust compute resources.
Chip Design Will Never Be the Same—and That’s a Good Thing
With increasingly complex designs, larger projects, and shorter timelines, engineers are starting to experience the productivity and time-to-market benefits of moving their workloads to the cloud. Given its vast compute resources, the cloud can handle the intensity and dynamic nature of electronic design cycles. Synopsys Cloud is changing this landscape with the highly flexible SaaS model. Large companies with their own data center infrastructure can supplement their own resources with on-demand cloud-optimized design and verification solutions. Smaller companies and startups can forgo the in-house IT investment and instead enjoy the flexibility of accessing compute and EDA resources as needed.
EDA on the cloud continues to be a journey, one that is only getting more interesting. With a SaaS model in the mix, chip and system design will never be the same, and that’s a welcome transformation.
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